The demand for more compact physical arrangements of microelectronic devices such as integrated chips has become even more intense with the rapid progress of portable electronic devices. Merely by way of example, devices commonly referred to as “smart phones” integrate the functions of a cellular telephone with powerful data processors, memory and ancillary devices such as global positioning system receivers, electronic cameras, and local area network connections along with high-resolution displays and associated image processing chips. Such devices can provide capabilities such as full interne connectivity, entertainment including full-resolution video, navigation, electronic banking and more, all in a pocket-size device. Complex portable devices require packing numerous chips into a small space.
Moreover, some of the chips have many input and output connections, commonly referred to as “I/O's.” These I/O's must be interconnected with the I/O's of other chips. The interconnections should be short and should have low impedance to minimize signal propagation delays. The components which form the interconnections should not greatly increase the size of the assembly.
One solution includes the use of build-up substrates or interposers, which route signals between chips and other board mounted systems, and provide for the use of small chips, as well as allow for vertical stacking of chips to maximize space efficiency. Various techniques can be used to form build-up microelectronic assemblies, which include a core, and have multiple built-up routing layers on either side of the core, with electrical interconnections between the layers. However, build-up substrates can be very expensive and are generally low yielding (sold as singulated units). In most cases, build-up substrates have few layers that can actually be used for routing, even if the substrate includes more layers. For instance, in some cases, 80-95% of the routing occurs above the core of the build-up substrate. Further, the thick cores common to build-up substrates can have negative system integration implications. For instance, it can be difficult to transmit high-frequency signals (e.g., 28 Gbps and above) due to large vias through the cores. This can limit the application of the build-up substrates.
Another challenge of multi-layer processing is to achieve a sufficiently planar interface between the layers of the build-up substrate and to make reliable electrical interconnections between contacts on respective layers.